I/O Completion Optimization & Storage Security 2023 – present
DPAS: Dynamic I/O Completion Method for SSDs
Dynamically switches among polling, interrupts, and an adaptive hybrid polling method (PAS) based on CPU contention levels, achieving both prompt and CPU-efficient I/O completion on modern SSDs.
- FAST 2026
- Artifact
- Demo
- US Patent 11,768,532
- US Patent App. 2026/0030187
- KR Patent 10-2919645
Virtualized I/O Performance Optimization
Expands the polled I/O path in the Linux kernel to improve I/O performance in virtualized environments, enabling efficient storage access for virtual machines.
Ransomware-Proof SSDs
A memory-efficient overwrite detection method that enables SSDs to detect and prevent ransomware encryption attacks at the firmware level.
I/O Reordering & Mobile Storage 2015 – 2020
I/O Reordering and Interleaving for Application Prefetching
Exploits both I/O reordering and I/O interleaving techniques to optimize application prefetcher design, improving launch performance on storage devices.
Mobile Application Loading Optimization
Enlarges I/O request sizes to reduce the number of I/O operations during mobile application loading, accelerating app launch on mobile storage.
SSD Performance & Nonvolatile Memory 2009 – 2014
FAST (Fast Application STarter)
An SSD-aware application launching scheme that overlaps CPU computation with I/O operations. Works on Linux systems without requiring kernel modifications.
SSD Parallelism Exploitation
An optimized application prefetcher for solid-state drives that exploits internal parallelism of SSDs to accelerate application launches.
IOLab: Active Storage Device Evaluation Platform
A virtual machine-based system that evaluates intelligence functions such as prefetching and data deduplication. The platform separates intelligence function implementation from specific operating systems using file-backed virtual disk images.
Hybrid Solid-State Storage Architecture
Combines phase change memory (PCM) and flash memory in a hybrid solid-state storage architecture to simultaneously improve performance, energy consumption, and device lifetime.
Hybrid PRAM and STT-RAM Cache Architecture
Extends phase change RAM (PRAM) cache lifespan by integrating spin transfer torque RAM (STT-RAM) write buffers through threshold-based ownership management.
Endurance-Aware PCM Cache Design
Addresses phase change memory limitations through write-traffic reduction techniques to improve both energy efficiency and device lifetime.
Hybrid Disk Block Allocation
Optimizes HDD and flash memory allocation for application launches by pinning selective subsequences to minimize seek time.
Energy-Efficient Memory Systems 2002 – 2008
Flash Memory Demand Paging & Energy Optimization
Designed energy- and performance-optimized demand paging for OneNAND flash-based execute-in-place systems, including delayed dual buffering to reduce page faults.
Energy-Aware Data Compression for MLC Flash
Developed energy-optimal prefix coding for multi-level cell flash memory that minimizes programming energy rather than compressed data size, using integer linear programming.
Low-Power SDRAM Memory Systems
Explored and reduced energy consumption of off-chip SDRAM memory systems for embedded applications through system-level energy characterization and optimization techniques.